so like, there!s errrors but idc and its late and im eepi

This commit is contained in:
benstrb 2026-04-06 00:33:46 +02:00
parent f7a83875aa
commit 242f218a62
15 changed files with 2920 additions and 2 deletions

0
.cargo/bin Normal file
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33
.cargo/config.toml Normal file
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[target.thumbv7m-none-eabi]
# uncomment this to make `cargo run` execute programs on QEMU
# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# uncomment ONE of these three option to make `cargo run` start a GDB session
# which option to pick depends on your system
# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
# runner = "gdb-multiarch -q -x openocd.gdb"
# runner = "gdb -q -x openocd.gdb"
rustflags = [
# LLD (shipped with the Rust toolchain) is used as the default linker
"-C", "link-arg=-Tlink.x",
# if you run into problems with LLD switch to the GNU linker by commenting out
# this line
# "-C", "linker=arm-none-eabi-ld",
# if you need to link to pre-compiled C libraries provided by a C toolchain
# use GCC as the linker by commenting out both lines above and then
# uncommenting the three lines below
# "-C", "linker=arm-none-eabi-gcc",
# "-C", "link-arg=-Wl,-Tlink.x",
# "-C", "link-arg=-nostartfiles",
]
[build]
# Pick ONE of these compilation targets
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
# target = "thumbv7m-none-eabi" # Cortex-M3
target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)

19
.direnv/bin/nix-direnv-reload Executable file
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#!/usr/bin/env bash
set -e
if [[ ! -d "/mnt/verbatim/projects/rust/stm32f469ni" ]]; then
echo "Cannot find source directory; Did you move it?"
echo "(Looking for "/mnt/verbatim/projects/rust/stm32f469ni")"
echo 'Cannot force reload with this script - use "direnv reload" manually and then try again'
exit 1
fi
# rebuild the cache forcefully
_nix_direnv_force_reload=1 direnv exec "/mnt/verbatim/projects/rust/stm32f469ni" true
# Update the mtime for .envrc.
# This will cause direnv to reload again - but without re-building.
touch "/mnt/verbatim/projects/rust/stm32f469ni/.envrc"
# Also update the timestamp of whatever profile_rc we have.
# This makes sure that we know we are up to date.
touch -r "/mnt/verbatim/projects/rust/stm32f469ni/.envrc" "/mnt/verbatim/projects/rust/stm32f469ni/.direnv"/*.rc

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/nix/store/8fwnz7i2qn0vki0rkmcic74dqfmxq2vj-source

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/nix/store/915fl6kpmx9i0dqas2b0bp5d19r9ksl3-source

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/nix/store/xaknai40sz4yyy5658prwrwmfycj4xvm-source

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/nix/store/6ijy66mcyfsd63dslwm7d554f2maz9pb-nix-shell-env

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40
.gdbinit Executable file
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target extended-remote :3333
# print demangled symbols
set print asm-demangle on
# set backtrace limit to not have infinite backtrace loops
set backtrace limit 32
# detect unhandled exceptions, hard faults and panics
break DefaultHandler
break HardFault
break rust_begin_unwind
# # run the next few lines so the panic message is printed immediately
# # the number needs to be adjusted for your panic handler
# commands $bpnum
# next 4
# end
# *try* to stop at the user entry point (it might be gone due to inlining)
break main
monitor arm semihosting enable
# # send captured ITM to the file itm.fifo
# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
# # 8000000 must match the core clock frequency
# monitor tpiu config internal itm.txt uart off 8000000
# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
# # 8000000 must match the core clock frequency
# # 2000000 is the frequency of the SWO pin
# monitor tpiu config external uart off 8000000 2000000
# # enable ITM port 0
# monitor itm port 0 on
load
# start the process but immediately halt the processor
stepi

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Cargo.lock generated Normal file
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# It is not intended for manual editing.
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View file

@ -4,3 +4,27 @@ version = "0.1.0"
edition = "2024"
[dependencies]
cortex-m = {version = "0.7.7", features = ["critical-section-single-core"]}
cortex-m-rt = "0.7.5"
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defmt-rtt = "1.1.0"
defmt = "1.0.1"
panic-probe = {version = "1.0.0", features = ["print-defmt"]}
[dependencies.stm32f4xx-hal]
version = "0.23.0"
features = ["stm32f469"]
[[bin]]
name = "stm32f469ni"
test = false
bench = false
[profile.dev]
panic = "abort"
[profile.release]
codegen-units = 1 # better optimizations
debug = false # symbols are nice and they don't increase the size on Flash
lto = true # better optimizations
panic = "abort"

View file

@ -18,10 +18,17 @@
devShells."${system}" = {
default = pkgs.mkShell {
buildInputs = with pkgs; [
rustup
gcc
gnumake
rust-bin.stable.latest.default
evcxr
openocd
gcc-arm-embedded
stlink
pkg-config
openssl
gdb
];
};
};

37
memory.x Normal file
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@ -0,0 +1,37 @@
MEMORY
{
/* NOTE 1 K = 1 KiBi = 1024 bytes */
/* STM32F302R8T6 from STM32F302R8Tx_FLASH.ld in the STM32Cube archive */
/* or the reference doc at */
/* https://www.st.com/en/microcontrollers-microprocessors/stm32f302.html#resource */
FLASH : ORIGIN = 0x08000000, LENGTH = 2M
RAM : ORIGIN = 0x20000000, LENGTH = 320k
}
/* This is where the call stack will be allocated. */
/* The stack is of the full descending type. */
/* You may want to use this variable to locate the call stack and static
variables in different memory regions. Below is shown the default value */
/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
/* You can use this symbol to customize the location of the .text section */
/* If omitted the .text section will be placed right after the .vector_table
section */
/* This is required only on microcontrollers that store some configuration right
after the vector table */
/* _stext = ORIGIN(FLASH) + 0x400; */
/* Example of putting non-initialized variables into custom RAM locations. */
/* This assumes you have defined a region RAM2 above, and in the Rust
sources added the attribute `#[link_section = ".ram2bss"]` to the data
you want to place there. */
/* Note that the section will not be zero-initialized by the runtime! */
/* SECTIONS {
.ram2bss (NOLOAD) : ALIGN(4) {
*(.ram2bss);
. = ALIGN(4);
} > RAM2
} INSERT AFTER .bss;
*/

12
openocd.cfg Executable file
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# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
# Depending on the hardware revision you got you'll have to pick ONE of these
# interfaces. At any time only one interface should be commented out.
# Revision C (newer revision)
source [find interface/stlink.cfg]
# Revision A and B (older revisions)
# source [find interface/stlink-v2.cfg]
source [find target/stm32f4x.cfg]

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@ -1,3 +1,49 @@
fn main() {
println!("Hello, world!");
#![no_std]
#![no_main]
use cortex_m_rt::entry;
use defmt_rtt as _;
use hal::prelude::*;
use panic_probe as _;
use stm32f4xx_hal as hal;
defmt::timestamp!("{=u32}", 0u32);
#[entry]
fn main() -> ! {
let peripherals = hal::pac::Peripherals::take().unwrap();
let mut rcc = peripherals.RCC.constrain();
let ltdc = peripherals.LTDC;
let dma2d = peripherals.DMA2D;
let display_config = hal::ltdc::DisplayConfig {
active_width: 480,
active_height: 800,
h_back_porch: 8,
h_front_porch: 8,
v_back_porch: 1,
v_front_porch: 1,
h_sync: 15,
v_sync: 60,
frame_rate: 5,
h_sync_pol: false,
v_sync_pol: false,
no_data_enable_pol: false,
pixel_clock_pol: false,
};
let display = hal::ltdc::DisplayController::new(
ltdc,
dma2d,
None,
hal::ltdc::PixelFormat::AL88,
display_config,
None,
);
let gpiog = peripherals.GPIOG.split(&mut rcc);
let mut led1 = gpiog.pg6.into_push_pull_output();
led1.set_high();
loop {}
}