all set up

This commit is contained in:
benstrb 2026-04-02 17:55:37 +02:00
parent db73deaa80
commit c7a5f98e54
15 changed files with 2833 additions and 3 deletions

0
.cargo/bin Normal file
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33
.cargo/config.toml Normal file
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[target.thumbv7m-none-eabi]
# uncomment this to make `cargo run` execute programs on QEMU
# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
# uncomment ONE of these three option to make `cargo run` start a GDB session
# which option to pick depends on your system
# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
# runner = "gdb-multiarch -q -x openocd.gdb"
# runner = "gdb -q -x openocd.gdb"
rustflags = [
# LLD (shipped with the Rust toolchain) is used as the default linker
"-C", "link-arg=-Tlink.x",
# if you run into problems with LLD switch to the GNU linker by commenting out
# this line
# "-C", "linker=arm-none-eabi-ld",
# if you need to link to pre-compiled C libraries provided by a C toolchain
# use GCC as the linker by commenting out both lines above and then
# uncommenting the three lines below
# "-C", "linker=arm-none-eabi-gcc",
# "-C", "link-arg=-Wl,-Tlink.x",
# "-C", "link-arg=-nostartfiles",
]
[build]
# Pick ONE of these compilation targets
# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
# target = "thumbv7m-none-eabi" # Cortex-M3
target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)

19
.direnv/bin/nix-direnv-reload Executable file
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#!/usr/bin/env bash
set -e
if [[ ! -d "/mnt/verbatim/projects/rust/nucleo" ]]; then
echo "Cannot find source directory; Did you move it?"
echo "(Looking for "/mnt/verbatim/projects/rust/nucleo")"
echo 'Cannot force reload with this script - use "direnv reload" manually and then try again'
exit 1
fi
# rebuild the cache forcefully
_nix_direnv_force_reload=1 direnv exec "/mnt/verbatim/projects/rust/nucleo" true
# Update the mtime for .envrc.
# This will cause direnv to reload again - but without re-building.
touch "/mnt/verbatim/projects/rust/nucleo/.envrc"
# Also update the timestamp of whatever profile_rc we have.
# This makes sure that we know we are up to date.
touch -r "/mnt/verbatim/projects/rust/nucleo/.envrc" "/mnt/verbatim/projects/rust/nucleo/.direnv"/*.rc

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/nix/store/fvb3fhm8c193i6692v5223bxpa5w2nv7-source

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/nix/store/k7k1h0pn4nsfjj3p9s8qijkbyaqvpa9g-source

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/nix/store/mwjp4gpq05h55cybmrxnrmhh7kmrpkws-source

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/nix/store/jz65zqx5dhp34j9f9ckw63a41dcrgwx1-nix-shell-env

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451
Cargo.lock generated Normal file
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# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 4
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"nb 1.1.0",
"num-traits",
"paste",
"rtcc",
"slice-group-by",
"stm32-usbd",
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@ -1,6 +1,26 @@
[package]
authors = ["{{authors}}"]
edition = "2018"
readme = "README.md"
name = "nucleo"
version = "0.1.0"
edition = "2024"
[dependencies]
cortex-m = {version = "0.7.7", features = ["critical-section-single-core"]}
cortex-m-rt = "0.7.5"
panic-halt = "1.0.0"
[dependencies.stm32f3xx-hal]
version = "0.10"
features = ["stm32f303xe"]
# this lets you use `cargo fix`!
[[bin]]
name = "nucleo"
test = false
bench = false
[profile.release]
codegen-units = 1 # better optimizations
debug = true # symbols are nice and they don't increase the size on Flash
lto = true # better optimizations

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@ -18,10 +18,17 @@
devShells."${system}" = {
default = pkgs.mkShell {
buildInputs = with pkgs; [
rustup
gcc
gnumake
rust-bin.stable.latest.default
evcxr
openocd
gcc-arm-embedded
stlink
pkg-config
openssl
gdb
];
};
};

37
memory.x Normal file
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MEMORY
{
/* NOTE 1 K = 1 KiBi = 1024 bytes */
/* STM32F302R8T6 from STM32F302R8Tx_FLASH.ld in the STM32Cube archive */
/* or the reference doc at */
/* https://www.st.com/en/microcontrollers-microprocessors/stm32f302.html#resource */
FLASH : ORIGIN = 0x08000000, LENGTH = 512K
RAM : ORIGIN = 0x20000000, LENGTH = 64K
}
/* This is where the call stack will be allocated. */
/* The stack is of the full descending type. */
/* You may want to use this variable to locate the call stack and static
variables in different memory regions. Below is shown the default value */
/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
/* You can use this symbol to customize the location of the .text section */
/* If omitted the .text section will be placed right after the .vector_table
section */
/* This is required only on microcontrollers that store some configuration right
after the vector table */
/* _stext = ORIGIN(FLASH) + 0x400; */
/* Example of putting non-initialized variables into custom RAM locations. */
/* This assumes you have defined a region RAM2 above, and in the Rust
sources added the attribute `#[link_section = ".ram2bss"]` to the data
you want to place there. */
/* Note that the section will not be zero-initialized by the runtime! */
/* SECTIONS {
.ram2bss (NOLOAD) : ALIGN(4) {
*(.ram2bss);
. = ALIGN(4);
} > RAM2
} INSERT AFTER .bss;
*/

12
openocd.cfg Normal file
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@ -0,0 +1,12 @@
# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
# Depending on the hardware revision you got you'll have to pick ONE of these
# interfaces. At any time only one interface should be commented out.
# Revision C (newer revision)
source [find interface/stlink.cfg]
# Revision A and B (older revisions)
# source [find interface/stlink-v2.cfg]
source [find target/stm32f3x.cfg]

40
openocd.gdb Normal file
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@ -0,0 +1,40 @@
target extended-remote :3333
# print demangled symbols
set print asm-demangle on
# set backtrace limit to not have infinite backtrace loops
set backtrace limit 32
# detect unhandled exceptions, hard faults and panics
break DefaultHandler
break HardFault
break rust_begin_unwind
# # run the next few lines so the panic message is printed immediately
# # the number needs to be adjusted for your panic handler
# commands $bpnum
# next 4
# end
# *try* to stop at the user entry point (it might be gone due to inlining)
break main
monitor arm semihosting enable
# # send captured ITM to the file itm.fifo
# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
# # 8000000 must match the core clock frequency
# monitor tpiu config internal itm.txt uart off 8000000
# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
# # 8000000 must match the core clock frequency
# # 2000000 is the frequency of the SWO pin
# monitor tpiu config external uart off 8000000 2000000
# # enable ITM port 0
# monitor itm port 0 on
load
# start the process but immediately halt the processor
stepi

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@ -1,3 +1,9 @@
fn main() {
println!("Hello, world!");
#![no_std]
#![no_main]
use core::ptr::write_volatile;
use cortex_m_rt::entry;
use panic_halt as _;
#[entry]
fn main() -> ! {
}